View LTC1983-3_196210.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LTC1983-3/LTC1983-5 100mA Regulated Charge-Pump Inverters in ThinSOT
FEATURES
s s s s s s s s s s
DESCRIPTIO
Fixed Output Voltages: -3V, -5V or Low Noise VIN to -VIN Inverted Output 4% Output Voltage Accuracy Low Quiesient Current: 25A 100mA Output Current Capability 3V to 5.5V Operating Voltage Range (LTC1983-3) 2.3V to 5.5V Operating Voltage Range (LTC1983-5) Internal 900kHz Oscillator "Zero Current" Shutdown Short-Circuit and Over-Temperature Protected Low Profile (1mm) ThinSOTTM Package
The LTC(R)1983-3 and LTC1983-5 are inverting charge pump DC/DC converters that produce negative regulated outputs. The parts require only three tiny external capacitors and can provide up to 100mA of output current. The devices can operate in open loop mode (creating a -VIN supply) or regulated output mode depending on the input supply voltage and the output current. The LTC1983-3/LTC1983-5 have many useful features for portable applications including very low quiescent current (25A typical) and a zero current shutdown mode programmed through the SHDN pin. The LTC1983-3/LTC1983-5 are over-temperature and short-circuit protected. The parts are available in a 6-pin low profile (1mm) ThinSOT package.
, LTC and LT are registered trademarks of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation.
APPLICATIO S
s s s s
-3V Generation in Single-Supply Systems Portable Equipment LCD Bias Supplies GaAs FET Bias Supplies
TYPICAL APPLICATIO
-3V at 100mA DC/DC Converter
VIN 3V TO 5.5V CIN 10F OFF ON VIN VOUT VOUT = -3V IOUT = UP TO 100mA COUT 10F VOUT (V) -3.3 -3.2 -3.1 -3.0 -2.9
LTC1983-3 SHDN C+ GND C-
1983-3 TA01
CFLY 1F CFLY: TAIYO YUDEN LMK212BJ105 CIN, COUT: TAIYO YUDEN JMK316BJ106ML
-2.8 -2.7
0
20
U
VOUT vs IOUT
VIN = 5V VIN = 3.3V 40 60 IOUT (mA) 80 100
1983 TA02
U
U
sn1983 1983fs
1
LTC1983-3/LTC1983-5
ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
ORDER PART NUMBER
TOP VIEW VCC 1 VOUT 2 C+ 3 6 SHDN 5 GND 4 C-
VIN to GND ................................................... -0.3V to 6V SHDN Voltage .............................................. -0.3V to 6V VOUT to GND (LTC1983-3) .................. 0.2V to VOUT Max VOUT to GND (LTC1983-5) .................. 0.2V to VOUT Max IOUT Max ............................................................. 125mA Output Short-Circuit Duration .......................... Indefinite Operating Temperature Range (Note 2) ...-40C to 85C Storage Temperature Range ................. - 65C to 125C Lead Temperature (Soldering, 10 sec).................. 300C
LTC1983ES6-3 LTC1983ES6-5 S6 PART MARKING LTPC LTYB
S6 PACKAGE 6-LEAD PLASTIC SOT-23 TJMAX = 125C, JA = 256C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 5V, CFLY = 1F, COUT = 10F unless otherwise noted.
PARAMETER VIN Operating Voltage (Regulated Output Mode) (LTC1983-3) VIN Min Startup Voltage VOUT (LTC1983-3) VOUT (LTC1983-5) VIN Operating Current VIN Operating Current (Open-Loop Mode) (LTC1983-5) VIN Shutdown Current Output Ripple Open-Loop Output Impedance (LTC1983-3): ROUT Open-Loop Output Impedance (LTC1983-5): ROUT Oscillator Frequency SHDN Input High SHDN Input Low SHDN Input Current Burst Mode is a registered trademark of Linear Technology Corporation. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. VSHDN = 5.5V VIN 3.3V, IOUT 25mA VIN 5V, IOUT 100mA VIN 5V, VIN -5V IOUT * ROUT VIN 5.5V, IOUT = 0A, SHDN = VIN VIN = 3.3V VIN = 4.75V SHDN = 0V, VIN 5.5V 3.3 VIN 5.5 VIN = 3.3V, VOUT = -3V VIN = 3.3V, IOUT 50mA VIN = 5V, IOUT 60mA (Non-Burst Mode(R) Operation)
q q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS
q q q q q
MIN 3.0 2.3 -2.88 -2.88 - 4.8
TYP
MAX 5.5
UNITS V V V V V A mA mA
-3 -3 -5 25 2.5 4 0.1 60 11 11 8.5 900
-3.12 -3.12 - 5.2 60
1
mVP-P kHz V 0.3 V A
1.1 2.2 4
Note 2: The LTC1983E-3/LTC1983E-5 are guaranteed to meet performance specifications from 0C to 70C. Specifications over the - 40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls.
sn1983 1983fs
2
U
A
W
U
U
WW
W
LTC1983-3/LTC1983-5 TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs IOUT (LTC1983-5)
90 80 70 VIN = 2.3V VIN = 5V VIN = 3.3V ROUT ()
EFFICIENCY (%)
60 50 40 30 20 10 0 0 20 60 40 IOUT (mA) TA = 25C 80 100
1983 G01
10.5 10.0 9.5 9.0 8.5 8.0 2.35 ROUT
ROUT ()
Efficiency vs IOUT
100 VOUT = -3V TA = 25C
-2.1
VIN = 3.3V
75
EFFICIENCY (%)
-2.7 80C -2.9 -3.1 -3.3 -40C, 0C, 40C
VOUT (-V)
VOUT (V)
50
25
0 0.01
0.1
1 IOUT (mA)
10
Open-Loop Current vs Temperature (LTC1983-5)
4.9 4.7 4.5
IIN (mA)
VIN = 5V
IIN (mA)
IIN (A)
4.3 4.1 3.9 3.7 3.5 -40
60 10 TEMPERATURE (C)
UW
VIN = 5V
1983 GO4
Output Impedance vs Input Voltage
12.5 12.0 11.5 11.0 IOUT = 25mA TA = 25C
Output Impedance vs IOUT (LTC1983-5)
30 TA = 25C VIN = 2.3V
25
20
15 VIN = 3.3V 10 VIN = 5V 5
3.35 VIN (V)
4.35
5.35
1983 TA02
0
20
60 40 IOUT (mA)
80
100
1983 G03
-3VOUT vs IOUT Over Temperature
3.3
-3VOUT vs IOUT Over Temperature (VIN = 5V)
VIN = 5V
-2.3 120C -2.5
3.2 3.1 -40C 0C 3.0 40C 2.9 80C 2.8 2.7
100
-3.5 0 20 80 60 100 40 OUTPUT CURRENT (mA) 120
1983 G05
0
20
40 60 80 100 OUTPUT CURRENT (mA)
120
1983 G06
Open-Loop Input Current vs VIN (LTC1983-5)
4.5 TA = 25C 4.0 3.5 3.0 2.5 2.0 1.5
50 45 40 35 30 25 20 15
Burst Mode Current vs Temperature (LTC1983-3)
VIN = 5V
110
1983 G07
2.3
2.8
3.3
3.3 VIN (V)
4.3
4.8
1983 G09
10 -40
10
60
110
1983 G08
TEMPERATURE (C)
sn1983 1983fs
3
LTC1983-3/LTC1983-5 TYPICAL PERFOR A CE CHARACTERISTICS
Burst Mode Input Current vs VIN (LTC1983-3)
31.0 30.5 30.0 TA = 25C 18 16 14
VTHRESHOLD (V)
INPUT CURRENT (A)
29.5 29.0 28.5 28.0 27.5 27.0 26.5 3.1 3.6 4.6 4.1 VIN (V) 5.1 5.5
ROUT ()
SHDN Pin Input Current vs Temperature
3.5 3.0 2.5 1400 1200 1000
ROUT ()
ISHDN
2.0 1.5 1.0 0.5 0 -50
0
100 TEMPERATURE (C)
50
VOUT Ripple at 100mA Load
VOUT 20mV
1s/DIV
4
UW
1983 G10 1983 G13
ROUT vs Temperature (IOUT = 10mA)
1.0
IOUT = 10mA
SHDN Pin Threshold Voltage vs Temperature
0.9 0.8
12 10 8 6 4 2 0 -50 0
VIN = 3V
0.7 0.6 0.5 0.4 0.3 0.2 0.1
VIN = 5V
100 TEMPERATURE (C)
50
150
1983 G11
0 -50
0
50 100 TEMPERATURE (C)
150
1983 G12
ROUT vs CFLY (VIN = 5V)
VIN = 5V TA = 25C
VOUT Start-Up into 100mA Resistive Load
VOUT 1V
800 600 400 200 0 0.01
VIN 5V
50s/DIV
1983 G15
150
0.1 CFLY (F)
1
1983 G14
VOUT Ripple at 30mA Load
VOUT Load Step Reponse from IOUT = 0 to IOUT = 100mA
VOUT 20mV
VOUT 20mV
IOUT 100mA 2.5s/DIV 100s/DIV
1983 G16
1983 G17
1983 G18
sn1983 1983fs
LTC1983-3/LTC1983-5
PI FU CTIO S
VIN (Pin 1): Charge Pump Input Voltage. May be between 2.3V and 5.5V. VIN should be bypassed with a 4.7F low ESR capacitor as close as possible to the pin for best performance. VOUT (Pin 2): Regulated Output Voltage for the IC. VOUT should be bypassed with a 4.7F low ESR capacitor as close as possible to the pin for best performance. C + (Pin 3): Charge Pump Flying Capacitor Positive Terminal. This node is switched between VIN and GND (It is connected to VCC during shutdown). C - (Pin 4): Charge Pump Flying Capacitor Negative Terminal. This node is switched between GND and VOUT (It is connected to GND during shutdown). GND (Pin 5): Signal and Power Ground for the 6-Pin SOT-23 package. This pin should be tied to a ground plane for best performance. SHDN (Pin 6): Shutdown. Grounding this pin shuts down the IC. Tie to VIN to enable. This pin should not be pulled above the VIN voltage or below GND.
BLOCK DIAGRA
C+
CFLY 1F
C-
CLOCK2
CHARGE PUMP COUT 10F
COMP1 1A
-
VOUT
S2B
+
W
U
U
U
LTC1983-X VIN CIN 10F
S1A
S2A
CLOCK1
SHDN CONTROL LOGIC
S1B
VREF
1983 BD
sn1983 1983fs
5
LTC1983-3/LTC1983-5
OPERATIO
The LTC1983-3/LTC1983-5 use a switched capacitor charge pump to invert a positive input voltage to a regulated -3V 4% (LTC1983-3) or -5 4% (LTC1983-5) output voltage. Regulation is achieved by sensing the output voltage through an internal resistor divider and enabling the charge pump when the output voltage droops above the upper trip point of COMP1. When the charge pump is enabled, a 2-phase, nonoverlapping clock controls the charge pump switches. Clock 1 closes the S1 switches which enables the flying capacitor to charge up to the VIN voltage. Clock 2 closes the S2 switches that invert the VIN voltage and connect the bottom plate of CFLY to the output capacitor at VOUT. This sequence of charging and discharging continues at a free-running frequency of 900kHz (typ) until the output voltage has been pumped down to the lower trip point of COMP1 and the charge pump is disabled. When the charge pump is disabled, the LTC1983 draws only 25A (typ) from VIN which provides high efficiency at low load conditions. In shutdown mode, all circuitry is turned off and the part draws less than 1A from the VIN supply. VOUT is also disconnected from VIN and CFLY. The SHDN pin has a threshold of approximately 0.7V. The part enters shutdown when a low is applied to the SHDN pin . The SHDN pin should not be floated; it must be driven with a logic high or low. Open-Loop Operation The LTC1983-3/LTC1983-5 inverting charge pumps regulate at -3V/-5V respectively, unless the input voltage is too low or the output current is too high. The equations for output voltage regulation are as follows: VIN -5.06V > IOUT * ROUT (LTC1983-5) VIN -3.06V > IOUT * ROUT (LTC1983-3) If this condition is not met, then the part will run in open loop mode and act as a low output impedance inverter for which the output voltage will be: VOUT = -[VIN -(IOUT * ROUT)]
6
U
(Refer to Block Diagram)
For all ROUT values, check the corresponding curves in the Typical Performance Characteristics section (Note: CFLY = 1F for all ROUT curves). The ROUT value will be different for different flying caps, as shown in the following equation:
1 ROUT = ROUT (curve ) - 1.11 + fOSC * C FLY
Short-Circuit/Thermal Protection During short-circuit conditions, the LTC1983 will draw several hundred milliamps from VIN causing a rise in the junction temperature. On-chip thermal shutdown circuitry disables the charge pump once the junction temperature exceeds 155C, and reenables the charge pump once the junction temperature falls back to 145C. The LTC1983 will cycle in and out of thermal shutdown indefinitely without latchup or damage until the VOUT short is removed. Capacitor Selection For best performance, it is recommended that low ESR capacitors be used for both CIN and COUT to reduce noise and ripple. The CIN and COUT capacitors should be either ceramic or tantalum and should be 4.7F or greater. Aluminum electrolytic are not recommended because of their high equivalent series resistance (ESR). If the source impedance is very low, CIN may not be needed. Increasing the size of COUT to 10F or greater will reduce output voltage ripple. The flying capacitor and COUT should also have low equivalent series inductance (ESL). The board layout is critical as well for inductance for the same reason (the suggested board layout should be used). A ceramic capacitor is recommended for the flying capacitor with a value in the range of 0.1F to 4.7F. Note that a large value flying cap (>1F) will increase output ripple unless COUT is also increased. For very low load applications, C1 may be reduced to 0.01F to 0.047F. This will reduce output ripple at the expense of efficiency and maximum output current.
sn1983 1983fs
LTC1983-3/LTC1983-5
OPERATIO
There are many aspects of the capacitors that must be taken into account. First, the temperature stability of the dielectric is a main concern. For ceramic capacitors, a three character code specifies the temperature stability (e.g. X7R, Y5V, etc.). The first two characters represent the temperature range that the capacitor is specified and the third represents the absolute tolerance that the capacitor is specified to over that temperature range. The ceramic capacitor used for the flying and output capacitors should be X5R or better. Second, the voltage coefficient of capacitance for the capacitor must be checked and the actual value usually needs to be derated for the operating voltage (the actual value has to be larger than the value needed to take into account the loss of capacitance due to voltage bias across the capacitor). Third, the frequency characteristics need to be taken into account because capacitance goes down as the frequency of oscillation goes up. Typically, the manufacturers have capacitance vs frequency curves for their products. This curve must be referenced to be sure the capacitance will not be too small for the application. Finally, the capacitor ESR and ESL must be low for reasons mentioned in the following section. Output Ripple Normal LTC1983 operation produces voltage ripple on the VOUT pin. Output voltage ripple is required for the LTC1983 to regulate. Low frequency ripple exists due to the hysteresis in the sense comparator and propagation delays in the charge pump enable/disable circuits. High frequency ripple is also present mainly due to ESR of the output capacitor. Typical output ripple under maximum load is 60mVP-P with a low ESR 10F output capacitor. The magnitude of the ripple voltage depends on several factors. High input voltage to negative output voltage differentials [(VIN + VOUT) >1V] increase the output ripple since more charge is delivered to COUT per clock cycle. A large flying capacitor (>1F) also increases ripple for the same reason. Large output current load and/or a small output capacitor (<10F)
U
(Refer to Block Diagram)
results in higher ripple due to higher output voltage dV/dt. High ESR capacitors (ESR > 0.1) on the output pin cause high frequency voltage spikes on VOUT with every clock cycle. There are several ways to reduce the output voltage ripple. A larger COUT capacitor (22F or greater) will reduce both the low and high frequency ripple due to the lower COUT charging and discharging dV/dt and the lower ESR typically found with higher value (larger case size) capacitors. A low ESR ceramic output capacitor will minimize the high frequency ripple, but will not reduce the low frequency ripple unless a high capacitance value is chosen. A reasonable compromise is to use a 10F to 22F tantalum capacitor in parallel with a 1F to 4.7F ceramic capacitor on VOUT to reduce both the low and high frequency ripple. However, the best solution is to use 10F to 22F, X5R ceramic capacitors which are available in 1206 package sizes. An RC filter may also be used to reduce high frequency voltage spikes (see Figure 1). In low load or high VIN applications, smaller values for CFLY may be used to reduce output ripple. A smaller flying capacitor (0.01F to 0.047F) delivers less charge per clock cycle to the output capacitor resulting in lower output ripple. However, the smaller value flying caps also reduce the maximum IOUT capability as well as efficiency.
LTC1983-X 3.9 VOUT 10F TANTALUM VOUT 10F TANTALUM
LTC1983-X VOUT 15F TANTALUM VOUT 1F CERAMIC
1983 F01
Figure 1. Output Ripple Reduction Techniques
sn1983 1983fs
7
LTC1983-3/LTC1983-5
OPERATIO
Inrush Currents During normal operation, VIN will experience current transients in the several hundred milliamp range whenever the charge pump is enabled. During start-up, these inrush currents may approach 1 to 2 amps. For this reason, it is important to minimize the source resistance between the input supply and the VIN pin. Too much source resistance may result in regulation problems or even prevent startup. One way that this can be avoided (especially when the source impedance can't be lowered due to system constraints) is to use a large VIN capacitor with low ESR right at the VIN pin. If ceramic capacitors are used, you may need to add 1F to 10F tantalum capacitor in parallel to limit input voltage transients. Input voltage transients will occur if VIN is applied via a switch or a plug. One example of this situation is in USB applications. Ultralow Quiescent Current Regulated Supply The LTC1983 contains an internal resistor divider (refer to the Block Diagram) that draws only 1A (typ for the 3V version) from VOUT during normal operation. During shutdown, the resistor divider is disconnected from the output and the part draws only leakage current from the output. During no-load conditions, applying a 1Hz to 100Hz, 2% to 5% duty cycle signal to the SHDN pin ensures that the circuit of Figure 2 comes out of shutdown frequently enough to maintain regulation even under low-load conditions. Since the part spends nearly all of its time in shutdown, the no-load quiescent current is essentially zero. However, the part will still be in operation during the time the SHDN pin is high, so the current will not be zero and can be calculated using the following equations to determine the approximate maximum current: IIN(MAX) = [(Time out of shutdown) * (Burst Mode operation quiescent current) + (Normal operating IIN) * (Time output is being charged before the LTC1983 enters Burst Mode operation)]/(Period of SHDN signal). This number will be highly dependent on the amount of board leakage current and how many devices are connected to VOUT (each will draw some leakage current) and must be calculated and verified for each different board design.
VIN CIN 10F TANTALUM
8
U
(Refer to Block Diagram)
3.3V TO 5.5V LTC1983-3 VIN SHDN GND C+ VOUT C- FROM MPU SHDN -3V 4% COUT 10F CERAMIC
CFLY 1F CERAMIC
SHDN PIN WAVEFORMS:
LOW IQ MODE (IOUT 100A)
VOUT LOAD ENABLE MODE (IOUT = 100A TO 100mA)
1983 F02
(1Hz TO 100Hz, 2% TO 5% DUTY CYCLE)
Figure 2. Ultralow Quiescent Current Regulated Supply
The LTC1983 must be out of shutdown for a minimum duration of 200s to allow enough time to sense the output and keep it in regulation. A 1Hz, 2% duty cycle signal will keep VOUT in regulation under no-load conditions. Even though the term no-load is used, there will always be board leakage current and leakage current drawn by anything connected to VOUT. This is why it is necessary to wake the part up every once in a while to verify regulation. As the VOUT load current increases, the frequency with which the part is taken out of shutdown must also be increased to prevent VOUT from drooping below the - 2.88V (for the 3V version) during the OFF phase (see Figure 3). A 100Hz, 2% duty cycle signal on the SHDN pin ensures proper regulation with load currents as high as 100A. When load current greater than 100A is needed, the SHDN pin must be forced high as in normal operation. Each time the LTC1983 comes out of shutdown, the part delivers a minimum of one clock cycle worth of charge to the output. Under high VIN (>4V) and/or low IOUT (<10A) conditions, this behavior may cause a net excess of charge to be delivered to the output capacitor if a high frequency signal is used on the SHDN pin (e.g., 50Hz to 100Hz). Under such conditions, VOUT will slowly drift positive and may even go out of regulation. To avoid this potential
sn1983 1983fs
LTC1983-3/LTC1983-5
OPERATIO
problem in the low IQ mode, it is necessary to switch the part in and out of shutdown at the minimum allowable frequency (refer to Figure 3) for a given output load. General Layout Considerations Due to the high switching frequency and high transient currents produced by the LTC1983, careful board layout is a must. A clean board layout using a ground plane and short connections to all capacitors will improve performance and ensure proper regulation under all conditions (refer to Figures 4a and 4b). You will not get advertised performance with careless layout.
MAXIMUM SHDN OFF TIME (ms)
U
(Refer to Block Diagram)
1000 SHDN ON PULSE WIDTH = 200s COUT = 10F
100
10
1 1 10 100 OUTPUT CURRENT (A) 1000
1983 F03b
Figure 3
VIN: 2.3V TO 5.5V
1 VOUT 2 3
VIN VOUT C+
SHDN GND C-
6 5 4
CIN
CFLY
COUT
1983 F04a
Figure 4a. Recommended Component Placement for a Single Layer Board
TOP LAYER
BOTTOM LAYER
1 VIN VOUT 2 VOUT 3 C+
SHDN 6 GND 5 C- 4
CIN
COUT
CFLY
1983 F04b
Figure 4b. Recommended Component Placement for a Double Layer Board
sn1983 1983fs
9
LTC1983-3/LTC1983-5
TYPICAL APPLICATIO S
2.5V to -2.5V DC/DC Converter
VIN 2.5V VIN 4.7F CERAMIC VOUT VOUT -2.5V 1F CERAMIC
VIN 2.5V TO 5.5V
10
U
LTC1983-5 SHDN C+ GND C-
OFF ON
1983 TA03
0.47F CERAMIC
100mA Inverting DC/DC Converter
VIN 10F CERAMIC VOUT 10F VOUT -VIN
LTC1983-5 SHDN C+ GND C-
OFF ON
1983 TA04
1F CERAMIC
sn1983 1983fs
LTC1983-3/LTC1983-5
PACKAGE DESCRIPTIO U
S6 Package 6-Lead Plastic SOT-23
(Reference LTC DWG # 05-08-1636)
2.90 BSC (NOTE 4) 0.754 0.854 0.127 2.80 BSC 1.50 - 1.75 (NOTE 4) PIN ONE ID 0.95 BSC 0.95 BSC 0.30 - 0.45 TYP 6 PLCS (NOTE 3) 0.80 - 0.90 0.20 BSC 1.00 MAX DATUM `A' 0.01 - 0.10 0.09 - 0.20 (NOTE 3) 1.90 BSC
S6 TSOT-23 0801
3.254
1.9 BSC RECOMMENDED SOLDER PAD LAYOUT
0.30 - 0.50 REF NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193
sn1983 1983fs
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LTC1983-3/LTC1983-5
TYPICAL APPLICATIO U
Combined Unregulated Doubler and Regulated Inverter
VIN VIN VOUT VOUT COUT1 10F CERAMIC CIN 10F CERAMIC LTC1983-3/ LTC1983-5 SHDN C+ D1 CBOOST 1F GND C- CFLY 1F CERAMIC D2 COUT2 10F CERAMIC
1983 TA05
OFF ON
VBOOST
VBOOST = 2VIN -2(VD)
RELATED PARTS
PART NUMBER LTC1261 LTC1261L LTC1429 LTC1514/LTC1515 LTC1516 LTC1522 LTC1550L/LTC1551L LT1611 LT1617/LT1617-1 LTC1682/-3.3/-5 LTC1751/-3.3/-5 LTC1754/-3.3/-5 LTC1928-5 LTC3200 DESCRIPTION Switched-Capacitor Regulated Voltage Inverter Switched-Capacitor Regulated Voltage Inverter Clock-Synchronized Switched-Capacitor Voltage Inverter Step-Up/Step-Down Switched-Capacitor DC/DC Converters Micropower Regulated 5V Charge Pump DC/DC Converter Micropower Regulated 5V Charge Pump DC/DC Converter 1.4MHz Inverting Mode Switching Regulator Micropower, Switched-Capacitor Voltage Inverter Doubler Charge Pumps with Low Noise LDO Doubler Charge Pumps Doubler Charge Pumps with Shutdown Doubler Charge Pump with Low Noise LDO Constant Frequency Doubler Charge Pump COMMENTS Selectable Fixed Output Voltages Adjustable and Fixed Output Voltages, Up to 20mA IOUT, MSOP Synchronizable Up to 2MHz System Clock VIN 2V to 10V, Adjustable or Fixed VOUT, IOUT to 50mA IOUT = 20mA (VIN 2V), IOUT = 50mA (VIN 3V) IOUT = 10mA (VIN 2.7V), IOUT = 20mA (VIN 3V) -5V at 150mA from a 5V Input, 5-Lead ThinSOT VIN 1.2V/1V to 15V; 350mA/100mA Current Limit MS8 and SO-8 Packages, IOUT = 80mA, Output Noise = 60VRMS VOUT =5V at 100mA; VOUT =3.3V at 80mA; ADJ; MSOP Packages ThinSOT Package; IQ = 13A; IOUT = 50mA ThinSOT Output Noise = 60VRMS; VOUT = 5V; VIN = 2.7V to 4V Low Noise, 5V Output or Adjustable
Low Noise, Switched-Capacitor Regulated Voltage Inverters 900kHz Charge Pump, 1mVP-P Ripple
sn1983 1983fs
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507 q www.linear.com
LT/TP 0302 2K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 2002

▲Up To Search▲

Price & Availability of LTC1983-3

	To Download LTC1983-3 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .